1. Field of the Invention
The present invention relates to a method of fabrication a mask for a LIGA process, and more specifically it relates to a method of fabricating a LIGA process mask that solves the problem of faulty mask patterns caused by partial peeling of the resist material layer, and that can be used in the mass production of semiconductor devices.
2. Description of the Related Art
The LIGA process, which takes its name from the German express Lithographie (lithography) Galvanoformung (electroplating) Abformung (molding) makes use of a mask that is fabricated by electroplating and x-rays with superior linearity that are produced by a synchrotron to produce a pattern having an ultra-high aspect ratio using lithography.
This technology is currently the subject of active research in Europe and the U.S.
Because this process enables the fabrication of a pattern having an extremely high aspect ratio (width of 2 xcexcm with a height of 100 xcexcm or greater), it enables the fabrication of ultra-small optical components and components for motors, for example.
Using the LIGA process, when patterning the resist, a mask is used that is similar to the type of mask used in x-ray lithography in the past.
In the LIGA process, however, whereas x-ray lithography was completed with an exposure time of approximately 10 seconds, because the resist is very thick, the thickness being in the range from 0.1 to 1 mm, the exposure time usually exceeds 1 hour, the result being that the absorbent element of the mask needs to have a thickness of approximately 10 xcexcm.
This is more than 10 times the thickness of the absorbent element in x-ray lithography, which is 1 xcexcm or less thick.
Next, the method of fabricating a LIGA process mask will be described, with reference made to FIG. 2. First, as shown in FIG. 2(a), an oxide film 12 is formed on one surface of a silicon substrate 11 and a nitride film 13 having a thickness of approximately 2 xcexcm is formed on the other surface thereof, and a plating seed layer 14 is formed on the nitride film 13 using, for example, deposition.
This plating seed layer 14 is formed by some type of electrically conductive material, such as by forming a chromium layer having a thickness of 100 Angstroms on the above-noted nitride film 13, and then laminating onto the chromium layer a metallic layer having a thickness of 2000 Angstroms.
Next, as shown in FIG. 2(b), a resist layer 15 having a thickness of 15 xcexcm (is applied to the seed layer 14, and patterning is done by exposure to ultraviolet light, so as to form the hollow portion of the pattern for plating, after which the silicon substrate 11 is immersed in a gold plating solution and agitated, with a voltage applied to it that is negative with respect to the plating solution so that, as shown in FIG. 2(c), a gold plating layer 16 having a thickness of 10 xcexcm, for example, is formed in the hollow parts of the plating pattern.
Next, after drying, resist peeling fluid is used to remove the resist 15, and an ion milling apparatus is used to remove the plating seed layer 14 that is not to be plated so that, as shown in FIG. 2(d), an absorbent element is formed from the lamination of the plating seed layer 14 and the gold plating layer 16.
Then, the oxide film 12 on the reverse surface is patterned, and the silicon substrate 11 is etched with this oxide film 12 used as a mask, thereby forming a nitride film membrane 17.
In the method of fabricating a LIGA process mask in the past, however, the following problems arise.
The first problem is that, with the shrinking of the hollow pattern size for plating, for example as shown in FIG. 3, parts 18 and 19 of the resist 15 peel away from the plating seed layer 14.
If gold plating is done in this condition, for example, gold will be deposited even in the peeled away parts 18 and 19 on the plating seed layer 14, resulting in a faulty mask pattern, the result being that the pattern fabricated by the LIGA is also faulty.
The second problem is that the large amount of gold that is used on the plating seed layer 14 causes a specific impurity potential to be imparted to the silicon substrate, the result being that, because this is a substance that is strictly controlled in a manufacturing process line for semiconductor devices, it was difficult in the past to make use of a LIGA process mask in the production of semiconductor devices.
The third problem is that, because when ultraviolet light is used for patterning of the resist 15, the height-to-width ratio (aspect ratio) of the plating hollow pattern that is formed was no more than 3 or 4, for a resist layer 15 having a thickness of 15 xcexcm, for example, the minimum width of the pattern that is formed is approximately 4 xcexcm.
The result of this was that it was not possible to apply the LIGA process to, for example, the case of patterning for an electrostatic micro-actuator, which develops a larger output the smaller is the spacing between two electrodes which apply a voltage, or to the case of manufacturing optical components for which alignment between a fiber and a laser must be made to a precision of 1 xcexcm or better.
Therefore, there was an urgent need in this field for a solution to the above-described problems.
The Japanese Unexamined Patent Publication (KOKAI)No. 4-150026 discloses the provision of a protective film on a film to be processed, for the purpose of preventing the removal of the film to be processed by etching during the patterning of a resist film of a semiconductor device.
However, the substance used in the present invention resists plating is not for the purpose of preventing etching, but rather a material that is selected because of its own property of resisting plating.
In this respect, it is intrinsically different from the protective film noted in the Japanese Unexamined Patent Publication (KOKAI)No. 4-150026, nor could the present invention be easily conceived of from the contents of the Japanese Unexamined Patent Publication (KOKAI)No. 4-150026.
In the Japanese Unexamined Patent Publication (KOKAI)No. 7-263379, there is a disclosure of the LIGA process itself, and in the Japanese Unexamined Patent Publication (KOKAI)No. 5-206125, there is a disclosure of a method for patterning a multilayer resist of a semiconductor device, and neither of these discloses the essence of the present invention.
Accordingly, it is an object of the present invention to improve on the above-described drawbacks of the prior art, by providing a LIGA process mask manufacturing method that achieves a solution to the problem of faulty mask patterns due to partial peeling of resist, and which also is usable in a process for manufacturing a semiconductor device and capable of forming a mask pattern having a high aspect ratio.
In order to achieve the above-noted object, the present invention adopts the following basic technical constitution.
Specifically, an embodiment of the present invention is a method for manufacturing a LIGA process mask, this method including a step of forming a plating seed layer on a substrate, a step of forming a layer made of a substance that resists plating over said plating seed layer, a step of forming a layer of resist material over said plating-resistant layer, a step of patterning said resist layer and said plating-resistant layer so as to form a plating pattern thereon, a step of plating inside of said plating pattern so as to form a plating layer on said plating seed layer, and a step of removing said resist layer, said plating-resistant layer and a non-plated part of said plating seed layer.
A method for manufacturing a LIGA process mask according to the present invention adopts the above-noted technical constitution, a feature of which is the formation of a layer of plating-resistance substance over the plating seed layer, so that even in the event that part of the layer of partially cooled resist peels away, because the plating-resistant layer remains on this part of the plating seed layer, the deposition of the plating layer is prevented, thereby preventing the occurrence of a faulty mask.
Additionally, because of the formation of a plating-resistant layer over the plating seed layer, contamination of a semiconductor device manufacturing process line by gold or the like that forms the plating seed layer is prevented, thereby making it possible to form and pattern the layer of resist material on a semiconductor device manufacturing process line.
Additionally, in order to increase the aspect ratio of the plating pattern that is formed, in performing the patterning process for such a layer made of resist material, even if an oxygen plasma that is one of methods which have been used in the past in anisotropic resist layer patterning, is used in place of ultraviolet light, because the etching does not reach the plating seed layer, resulting in a change in the quality of the plating seed layer, it is sufficiently possible to use anisotropic etching.
In the case in which the plating in the present invention is gold plating, it is desirable that the plating-resistant substance used be a metallic nitride that either partially or completely resists plating, and the use of titanium nitride, which is often used in semiconductor device manufacturing processes is further preferable, since it enables the formation and patterning of the resist layer on a semiconductor device manufacturing process line.
In the present invention, the plating pattern which will be formed inside the resist layer is preferably a hollow configuration.
Another substance that can be used as plating-resistant substance is an electrical insulating material that either partially or completely resists electroplating.
Of such materials, if a silicon oxide, a silicon nitride, BPSG, TEOS or such inorganic or organic insulation film materials as used in semiconductor device manufacturing processes can be used, and the use of a silicon oxide or silicon nitride in particular is more preferable, since it enables the formation and patterning of the resist layer on a semiconductor device manufacturing process line.
When a semiconductor device manufacturing process line is used to form and pattern the resist material layer, because it is possible to use a resist material that is used in, for example, a two-layer or a three-layer resist, this presents an advantage, since the patterning of this resist material layer can be done by etching technology which makes use of semiconductor device manufacturing processes such oxygen plasma etching, and in particular anisotropic etching technology.